1. Field of the Invention
The present invention relates to a microcomputer, and, more particularly, to a microcomputer containing as nonvolatile memory therein an electrically erasable and programmable read-only memory (EEPROM), more particularly a batch erasable flash EEPROM.
2. Description of the Related Art
As related art of flash EEPROMs, Japanese Patent Application Laid-Open Hei 5-266219 proposes the configuration of a microcomputer containing therein a central processing unit (CPU), a random access memory (RAM), and a flash EEPROM, wherein the microcomputer can perform various operations by rewriting or changing contents of storage such as programs, data or the like stored in the flash EEPROM while it is mounted in a system unit.
The above patent application discloses configurations of a first microcomputer only having a flash EEPROM in which the flash EEPROM is used in place of a read-only memory (ROM), and a second microprocessor having a ROM in addition to the flash EEPROM.
Both microcomputers have two different modes of a mode rewriting the flash EEPROM under write control of the CPU (hereinafter called the "CPU rewrite control mode"), and a mode rewriting it under control of an external device such as a general purpose PROM writer (hereinafter called the "external rewrite control mode").
Here, it is possible to properly use the modes in such a manner that the external rewrite control mode is mainly applied to writing of initial data and initial programs related to mount the microcomputer on the system, while the CPU rewrite control mode is used for a case in tuning data or debugging the programs while running the microcomputer.
More specifically, in the case of external rewrite mode, for both the first and second microcomputers, the flash EEPROM becomes a state where it can be directly accessed by the general purpose PROM writer externally provided, and other components such as the CPU not relating to rewrite control of the EEPROM becomes a state where they are disconnected from the flash EEPROM.
On the other hand, in the case or CPU rewrite control mode, for the first microcomputer, the contents of storage of the flash EEPROM is rewritten under control of the CPU. In this case, a rewrite control program and a transfer control program are previously written in a predetermined region of the flash EEPROM, and the CPU executes the transfer control program to transfer the rewrite control program to the RAM. After completion of transfer, the process on the CPU proceeds to execute the rewrite control program on the RAM, whereby erase or write is performed for the flash memory. On the other hand, the second microcomputer stores in a mask ROM data and programs which are not necessary to be rewritten. In the CPU rewrite control mode, the CPU performs control for erase or write for the flash EEPROM according to a rewrite control program written in the flash EEPROM, or a rewrite control program stored in the mask ROM.
Here, codes for write in the flash EEPROM are received by using an interface function contained the first and second microcomputers.
However, there are various interfaces to be connected to such microcomputers, and, if the interfaces to be connected is limited to a built-in interface, it cannot fully meet demands of the user.
In addition, the erase/write program for the flash EEPROM requires a complicated erase/write procedure. Since details of such procedure is typically changed in response to change of manufacturing conditions for devices including the flash EEPROM, when the first microcomputer is used, if a device manufacturer changes its design or manufacturing conditions, the user is forced to change the erase/write procedure for such changed conditions.
On the other hand, the second microcomputer cannot meet changes of the ROM program for erasing or writing the flash EEPROM.
Then, to solve such problems, a microcomputer has proposed which is comprising an EEPROM, being capable of meeting various interfaces, and of selectively changing over between a mode for erasing or writing the EEPROM by fixedly executing a program on a ROM through use of a standardized built-in interface (hereinafter called the "exclusive program mode"), and a mode for modifying parts or all of user programs stored in the flash EEPROM by executing a program other than that on the ROM (hereinafter called the "user program mode"), and making both modes the CPU rewrite control programs, thereby minimizing a RAM area occupied by programs being down loaded.
In the microcomputer described in the related application, when the device manufacturer incorporates the erase/write program for flash EEPROM relating to the design and manufacturing conditions specific to the device as a one specific for the device during its manufacturing phase in a form of mask ROM or the like, the user is released from burden on change of the erase/write program due to a change by the device manufacturer.
In addition, the microcomputer described in the related application comprises a flash EEPROM, and a ROM containing an erase/write procedure for the EEPROM, wherein switching between the flash EEPROM and the ROM is not only performed with the state of an external terminal in resetting but also can be implemented by an exclusive register controllable by the CPU. Since the exclusive program mode and the user program mode can be changed over each other by setting of the exclusive register, the ROM can be directly accessed from the CPU in the user program mode. This causes the erase/write operation for the flash EEPROM in each mode as follows.
First, the ROM contains the erase/write program for flash EEPROM specific to the microcomputer, while the flash EEPROM contains a user program and a communication control program used by the user program. The communication control program is to receive rewrite data for the flash EEPROM from outside. In this state, when the exclusive program mode is set by setting of the external terminal, after resetting is released, the CPU fixedly executes the erase/write program for EEPROM stored in the ROM to erase or write the flash EEPROM. The operation for executing the program stored in the ROM in this manner is called a "first mode."
On the other hand, in the user program mode after the user program is once written in the flash EEPROM, after resetting is released, the CPU executes the user program written in the flash EEPROM. Then, if it is necessary to rewrite a part of the user program for tuning or the like, the communication control program stored in the flash EEPROM and the program for switching between the flash EEPROM and the ROM (an exclusive register setting instruction or the like) are transferred to the RAM, and then the erase or write operation is executed according to information such as addresses, data and parameters transferred to the RAM. Such operation according to information other than the program stored in the ROM is called a "second mode." The second mode uses the program transferred to the RAM to set the exclusive register under control of the CPU, and to access the ROM containing the erase/write procedure for the flash EEPROM therein.
As described, since the second mode of the microcomputer can use the erase/write procedure for flash EEPROM stored in the ROM, it does not require, as in the microcomputer described in Japanese Patent Application Laid-Open No. 5-266219, to previously download to the RAM all of a program for executing external to the ROM or chip the erase/write procedure for flash EEPROM (rewrite control program), and a program containing a communication protocol with a host device external to the chip for providing write codes (communication control program).
Now, the operation of the microcomputer describes with reference to FIGS. 9-15.
Referring to FIG. 9, a microcomputer 14 comprises a CPU 5, a flash EEPROM 2, a ROM 3 storing an erase/write procedure, a RAM 16 capable of fetching, a change-over switch 15, a serial interface (hereinafter called the "serial I/F") 7 for transmitting and receiving data to and from outside, a reset or RS terminal 26, an external or EX terminal 28, and a supply voltage or VPP terminal 29 for the flash EEPROM. In addition, provided external to the microcomputer 14 is an external host device 9 such as a PROM writer storing an application program. Here, the application program means to be a program usually used for controlling hardware or performing data processing, and for rewriting the flash EEPROM.
Referring to FIGS. 10 and 11, the change-over switch 15 comprises an exclusive register 17 (one bit), a latch circuit 18 for latching a logical value of the EX terminal 28 when the RS terminal 26 rises, and an OR gate 24 with output of the exclusive register 17 and output of the latch circuit 18 as its inputs. Output of the OR gate 24 is directly connected to the ROM 3 as a CS (chip select) signal 37, and to the flash EEPROM 2 through an invertor 25 as CS.sup.- signal 38 (symbol .sup.- indicating inversion). Thus, it is possible to exclusively select either one of the flash EEPROM 2 or the ROM 3 with the CS.sup.- signal 38 of the CS signal 37. FIGS. 10 and 11 are divided for the convenience of preparation of drawings.
Referring to FIG. 9, the ROM 3 stores an erase/write procedure for EEPROM (EEPROM write control program which can be commonly used for the first and second modes, and a communication control program for controlling communication (receiving) of write data. In addition, the exclusive programming mode is specified by latching state "1" of the EX terminal 28 with the latch circuit 18, or by setting a logical value "1" in the exclusive register 17 from the CPU 5. In this case, the CS signal 37 becomes the high level, and the CS.sup.- signal 38 becomes the low level, so that the ROM 3 is selected.
When the latch circuit 18 latches a logical value "1," the microcomputer 14 becomes the first mode, wherein, as shown in FIGS. 12 and 13, the CPU 5 fixedly executes the EEPROM rewrite control program stored in the ROM 3 to perform erase or write to the flash EEPROM 2. That is, in the first mode, the flash EEPROM 2 is accessed as a peripheral device by the CPU 5. FIGS. 12 and 13 are divided for the convenience of preparation of drawings.
On the other hand, when the latch circuit 18 latches a logical value "0," the microcomputer 14 becomes the user program mode. When a program in the flash EEPROM 2 is rewritten by a user program therein, it becomes the second mode. In this case, the CS signal 37 become the low level, and the CS.sup.- signal 38 becomes the high level, so that the flash EEPROM 2 is selected.
In the second mode, the microcomputer 14 transmits and receives the application program stored in the external host device 9 using communication means such as the serial I/F 7 in the user program mode (1), as shown in FIGS. 14 and 15. Subsequently, after downloaded to the RAM 16 capable of fetching are the program for changing over the flash EEPROM 2 and the ROM 3 in a user program stored in the flash EEPROM 2, and information such as addresses, data and parameters necessary for rewriting the flash EEPROM 2, the process branches to the RAM 16 (see (2) in FIGS. 14 and 15), and the logic of the exclusive register 17 is set to "1" by the transferred program for switching between the flash EEPROM 2 and the ROM 3, so that it transfers to the exclusive program mode (see (3) in FIGS. 14 and 15). In this case, the CS signal 37 become the high level, and the CS.sup.- signal 38 becomes the low level, so that the ROM 3 is selected. FIGS. 14 and 15 are divided for the convenience of preparation of drawings.
Thereafter, the process branches to the ROM 3 in which the erase/write procedure for EEPROM is stored to execute the erase/write operation of the flash EEPROM 2 (see (4) in FIGS. 14 and 15).
After completion of rewrite, the process branches again to the RAM 16 (see (5) in FIGS. 14 and 15), and sets the logic of the exclusive register to "0," so that it transfers to the user program mode (see (6) in FIGS. 14 and 15).
Then, it returns to the normal operation mode, whereby the rewritten application program in the flash EEPROM starts to be executed (see (7) in FIGS. 14 and 15).
That is, since, in the second mode, the program erase/write program can be commonly used with the program of the first mode, the required capacity of RAM 16 capable of fetching can be reduced by the amount which is saved by the fact that the flash write control program is not necessary to be transferred to the RAM in tuning the user program.
However, since the microcomputer containing the flash EEPROM therein which performs erase and write with the above-described erase/write method exclusively changes over the flash EEPROM in the user program mode, when the user wished to change the program, he/she must once download the program for switching between the flash EEPROM and the ROM, and information such as addresses, data and parameters necessary for rewriting the flash EEPROM from the flash EEPROM to the RAM before performing the erase/write operation according to the information. Thus, it has a problem that it must contains a programmable RAM, or connect an external memory.
Furthermore, capacity of the RAM should be larger than size of a program and data to be transferred. In addition, since the program is evacuated to the RAM, it also takes time in switching between the flash EEPROM and the ROM.